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LM5066PMHX Datasheet(PDF) 10 Page - Texas Instruments |
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LM5066PMHX Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 65 page  SCL VIH VIL VIH VIL P S S P SDA tHD;DAT tSU;STO tHD;STA tSU;STA tSU;DAT tHIGH tBUF tLOW tR tF 10 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Product Folder Links: LM5066 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated (1) Devices participating in a transfer will timeout when any clock low exceeds the value of tTIMEOUT,MIN of 25 ms. Devices that have detected a timeout condition must reset the communication no later than tTIMEOUT,MAX of 35 ms. The maximum value must be adhered to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms). (2) tHIGH MAX provides a simple method for devices to detect bus idle conditions. (3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a slave exceeds this time, it is expected to release both its clock and data lines and reset itself. (4) tLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack, or ack-to-stop. (5) Rise and fall time is defined as follows: tR = ( VILMAX – 0.15) to (VIHMIN + 0.15); tF = 0.9 VDD to (VILMAX – 0.15) 7.6 SMBus Communications Timing Requirements and Definitions PARAMETER MIN MAX UNIT ƒSMB SMBus operating frequency 10 400 kHz tBUF Bus free time between stop and start condition 1.3 µs tHD:STA Hold time after (repeated) start condition. After this period, the first clock is generated. 0.6 µs tSU:STA Repeated start condition setup time 0.6 µs tSU:STO Stop condition setup time 0.6 µs tHD:DAT Data hold time 85 ns tSU:DAT Data setup time 100 ns tTIMEOUT Clock low time-out(1) 25 35 ms tLOW Clock low period 1.5 µs tHIGH Clock high period(2) 0.6 µs tLOW:SEXT Cumulative clock low extend time (slave device)(3) 25 ms tLOW:MEXT Cumulative low extend time (master device)(4) 10 ms tF Clock or data fall time(5) 20 300 ns tR Clock or data rise time(5) 20 300 ns Figure 1. SMBus Timing Diagram |
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