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SP3232BCP Datasheet(PDF) 11 Page - Sipex Corporation |
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SP3232BCP Datasheet(HTML) 11 Page - Sipex Corporation |
11 / 18 page 11 Rev. 6/30/03 SP3222B/3232B True +3.0 to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Si- multaneous with the transfer of the voltage to C 4, the positive side of capacitor C1 is switched to V CC and the negative side is connected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the inter- nal oscillator are present. Since both V+ and V– are separately generated from V CC; in a no–load condition V + and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as 0.1 µF with a 16V breakdown voltage rating. ESD Tolerance The SP3222B/3232B series incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electrostatic discharges and associated transients. The Human Body Model has been the generally accepted ESD testing method for semiconduc- tors. This method is also specified in MIL-STD- 883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s potential to store electrostatic energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 18. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently. For the Human Body Model, the current limiting resistor (R S) and the source capacitor (C S) are 1.5kΩ and 100pF, respectively. Figure 13. Charge Pump — Phase 1 Figure 14. Charge Pump — Phase 2 VCC = +5V –5V –5V +5V VSS Storage Capacitor VDD Storage Capacitor C1 C2 C3 C4 + + ++ – – – – VCC = +5V –10V VSS Storage Capacitor VDD Storage Capacitor C1 C2 C3 C4 + + ++ – – – – |
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