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LMZ34202

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SNVSAJ2 – MARCH 2016

Product Folder Links: LMZ34202

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Copyright © 2016, Texas Instruments Incorporated

(1)

G = Ground, I = Input, O = Output

5 Pin Configuration and Functions

RVQ Package

43-Pin QFN

(Top View)

Pin Functions

PIN

DESCRIPTION

NAME

NO.

AGND

1, 2, 3, 4,

5, 11, 12

G

Zero volt reference for the analog control circuitry. All of these pins are not connected together

internal to the device and must be connected to one another externally using an analog ground

plane on the PCB. Pins 11 and 12 are internally connected to the PGND of the device at a single

point. The analog ground plane of the PCB should allow only analog ground currents to flow through

these pins.

CLK

8

I

Synchronization input to synchronize the device to an external clock. Connect this pin to AGND if

not used.

DNC

6, 40

-

Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage.

These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.

INH/UVLO

26

I

Inhibit and UVLO adjust pin. Use an open drain or open collector device to control the inhibit

function. A resistor divider between this pin, AGND, and PVIN adjusts the UVLO voltage. Connect

this pin to PVIN if not used.

PGND

19, 29, 30,

31, 32, 33,

41

G

This is the return current path for the power stage of the device. Connect these pins to the input

source, the load, and to the bypass capacitors associated with PVIN and VOUT using power ground

planes on the PCB. Pad 41 should be connected to the ground planes using multiple vias for good

thermal performance.

PH

34, 35, 36,

37, 38, 39

O

Phase switch node. Do not place any external components on these pins or tie them to a pin of

another function.

PVIN

27, 28, 42

I

Power input voltage. These pins supply all of the power to the device. Connect these pins to the

input source and connect external bypass capacitors between these pins and PGND close to the

device.

PWRGD

20

O

Power Good flag pin. This open drain output asserts low if the output voltage is more than

approximately ±10% out of regulation. This pin is internally connected to an uncommitted 100k pull-

up resistor that can be pulled up to a user-defined voltage applied to the PWRGD_PU pin.