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AD9993BBCZRL Datasheet(PDF) 6 Page - Analog Devices

Part # AD9993BBCZRL
Description  Integrated Mixed-Signal Front End (MxFE)
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9993BBCZRL Datasheet(HTML) 6 Page - Analog Devices

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AD9993
Data Sheet
Rev. A | Page 6 of 56
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CLOCK INPUT (CLKP, CLKN)
Differential Peak to Peak Voltage
350
mV
Common Mode Voltage
1.2
V
Master Clock Frequency
200
1000
MHz
REFCLK Input (REFCLK)
Input VIN Logic High
1.8
V
Input VIN Logic Low
0.0
V
REFCLK Frequency
31.25 or
62.5
MHz
SERIAL PERIPHERAL INTERFACE (SPI)
SPI_SCLK Frequency
25
MHz
SPI_SCLK Pulse Width High
10
ns
SPI_SCLK Pulse Width Low
10
ns
Setup Time, SPI_SDI to SPI_SCLK Rising
Edge
2
ns
Hold Time, SPI_SCLK Rising Edge to
SPI_SDI
2
ns
Setup Time, SPI_CS to SPI_SCLK Rising
Edge
2
ns
Hold Time, SPI_SCLK Rising Edge to
SPI_CS
2
ns
Data Valid, SPI_SCLK Falling Edge to
SPI_SDO
2
ns


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