Electronic Components Datasheet Search |
|
DVGA2-33 Datasheet(PDF) 8 Page - Mini-Circuits |
|
DVGA2-33 Datasheet(HTML) 8 Page - Mini-Circuits |
8 / 9 page Digital Controlled Variable Gain Amplifier (DVGA) DVGA2-33+ Page 8 Notes A. Performance and quality attributes and conditions not expressly stated in this specification document are intended to be excluded and do not form a part of this specification document. B. Electrical specifications and performance data contained in this specification document are based on Mini-Circuit’s applicable established test performance criteria and measurement instructions. C. The parts covered by this specification document are subject to Mini-Circuits standard limited warranty and terms and conditions (collectively, “Standard Terms”); Purchasers of this part are entitled to the rights and benefits contained therein. For a full statement of the Standard Terms and the exclusive rights and remedies thereunder, please visit Mini-Circuits’ website at www.minicircuits.com/MCLStore/terms.jsp Mini-Circuits® www.minicircuits.com P.O. Box 350166, Brooklyn, NY 11235-0003 (718) 934-4500 sales@minicircuits.com The DVGA2-33+, uses a common 6-bit serial, as shown in Table 4: 6-Bit attenuator Serial Programming Register Map. The first bit, the MSB, corresponds to the 16-dB Step and the last bit, the LSB, corresponds to the 0.5dB step. The DVGA2-33+ always assumes a specifiable attenuation setting on power-up, allowing a known attenuation state to be established before an initial serial control word is provided. When the attenuator powers up, the six control bits are set to whatever data is present on the six control inputs (C0.5 to C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. Power-up Control Settings Table 4. 6-Bit attenuator Serial Programming Register Map B5 B4 B3 B2 B1 B0 C16 C8 C4 C2 C1 C0.5 MSB (first in) LSB (last in) Figure 4. Serial Interface Timing Diagram Table 3. Serial Interface AC Characteristics (VD1=3V) Symbol Parameter Min. Max. Units f clk Serial data clock frequency (Note 1) 10 MHz t clkH Serial clock HIGH time 30 ns t clkL Serial clock LOW time 30 ns t LESUP LE set-up time after last clock falling edge 10 ns t LEPW LE minimum pulse width 30 ns t SDSUP Serial data set-up time before clock rising edge 10 ns t SDHLD Serial data hold time after clock falling edge 10 ns Note 1. fclk verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10MHz to verify fclk speci- fication. LE Clock Data MSB LSB t LESUP t SDSUP tSDHLD t LEPW |
Similar Part No. - DVGA2-33 |
|
Similar Description - DVGA2-33 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |