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DVGA2-33 Datasheet(PDF) 7 Page - Mini-Circuits |
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DVGA2-33 Datasheet(HTML) 7 Page - Mini-Circuits |
7 / 9 page Digital Controlled Variable Gain Amplifier (DVGA) Page 7 DVGA2-33+ Notes A. Performance and quality attributes and conditions not expressly stated in this specification document are intended to be excluded and do not form a part of this specification document. B. Electrical specifications and performance data contained in this specification document are based on Mini-Circuit’s applicable established test performance criteria and measurement instructions. C. The parts covered by this specification document are subject to Mini-Circuits standard limited warranty and terms and conditions (collectively, “Standard Terms”); Purchasers of this part are entitled to the rights and benefits contained therein. For a full statement of the Standard Terms and the exclusive rights and remedies thereunder, please visit Mini-Circuits’ website at www.minicircuits.com/MCLStore/terms.jsp Mini-Circuits® www.minicircuits.com P.O. Box 350166, Brooklyn, NY 11235-0003 (718) 934-4500 sales@minicircuits.com The serial interface is a 6-bit serial in, parallel-out shift register buffered by a transparent latch. It is controlled by three CMOS-compatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The timing for this operation is defined by Figure 4 (Serial Interface Timing Diagram) and Table 3 (Serial Interface AC Characteristics). Simplified Schematic Table 2. Truth Table Attenuation State C16 C8 C4 C2 C1 C0.5 Reference 0 0 0 0 0 0 0.5 (dB) 0 0 0 0 0 1 1 (dB) 0 0 0 0 1 0 2 (dB) 0 0 0 1 0 0 4 (dB) 0 0 1 0 0 0 8 (dB) 0 1 0 0 0 0 16 (dB) 1 0 0 0 0 0 31.5 (dB) 1 1 1 1 1 1 Note: Not all 64 possible combinations of C0.5 - C16 are shown in table Figure 3. The DVGA2-33+ Serial interface consists of 6 control bits that select the desired attenuation state, as shown in Table 2 Truth Table. |
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