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97240-11 Datasheet(PDF) 7 Page - Peregrine Semiconductor |
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97240-11 Datasheet(HTML) 7 Page - Peregrine Semiconductor |
7 / 21 page Page 7 of 21 Document No. DOC-15214-7 │ www.e2v-us.com ©2010-2015 Peregrine Semiconductor Corp. All rights reserved. Product Specification PE97240 Table 6. AC Characteristics @ VDD = 2.7V, –40 °C < TA < +85 °C, unless otherwise specified (continued) Symbol Parameter Condition Min Typical Max Unit SSB phase noise 5/6 prescaler (FIN = 3 GHz, PF_R = +5 dBm, fC = 50 MHz, LBW = 500 kHz) N Phase noise 100 Hz offset –100 –92 dBc/Hz N Phase noise 1 kHz offset –109 –103 dBc/Hz N Phase noise 10 kHz offset –116 –110 dBc/Hz N Phase noise 100 kHz offset –118 –115 dBc/Hz SSB phase noise 10/11 prescaler (FIN = 3 GHz, PF_R = +5 dBm, fC = 50 MHz, LBW = 500 kHz) N Phase noise 100 Hz offset –98 –91 dBc/Hz N Phase noise 1 kHz offset –104 –98 dBc/Hz N Phase noise 10 kHz offset –111 –107 dBc/Hz N Phase noise 100 kHz offset –117 –113 dBc/Hz Phase noise figure of merit (FOM)6 FOMflicker Flicker figure of merit 5/6 prescaler –268 –265 dBc/Hz 10/11 prescaler –263 –259 dBc/Hz FOMfloor Floor figure of merit 5/6 prescaler –230 –227 dBc/Hz 10/11 prescaler –229 –225 dBc/Hz FOMflicker PNflicker = FOMflicker + 20log (FIN) – 10log (foffset) dBc/Hz FOMfloor PNfloor = FOMfloor + 10log (fc) + 20log (FIN/fc) dBc/Hz FOMtotal dBc/Hz PNtotal = 10log (10 [PNflicker/10] + 10 [PNfloor/10]) Notes: 1. Timing parameters are guaranteed through design characterization and not tested in production. 2. fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. 3. 0 dBm minimum is recommended for improved phase noise performance when sine-wave is applied. 4. CMOS logic levels can be used to drive the reference input. If the VDD of the CMOS driver matches the VDD of the PLL IC, then the reference input can be DC coupled. Otherwise, the reference input should be AC coupled. For sine-wave inputs, the minimum amplitude needs to be 0.5 VPP. The maximum level should be limited to prevent ESD diodes at the pin input from turning on. Diodes will turn on at one forward-bias diode drop above VDD or below GND. The DC voltage at the Reference input is VDD/2. 5. +2 dBm or higher is recommended for improved phase noise performance. 6. The phase noise can be separated into two normalized specifications: a floor figure of merit and a flicker figure of merit. To accurately measure the phase noise floor without the contribution of the flicker noise, the loop bandwidth is set to 500 kHz and the phase noise is measured at a frequency offset near 100 kHz. The flicker noise is measured at a frequency offset ≤1000 Hz. The formula assumes a –10 dB/decade slope versus frequency offset. |
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