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ATTINY2313 Datasheet(PDF) 40 Page - ATMEL Corporation

Part No. ATTINY2313
Description  8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash
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Maker  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
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ATtiny2313/V
2543C–AVR–12/03
bit must also be set when changing the prescaler bits. See “Timed Sequences for
Changing the Configuration of the Watchdog Timer” on page 43.
• Bit 3 – WDE: Watchdog Enable
When WDE is written to logic one, the Watchdog Timer is enabled, and if WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the
WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following pro-
cedure must be followed:
1.
In the same operation, write a logic one to WDCE and WDE. A logic one must be
written to WDE even though it is set to one before the disable operation starts.
2.
Within the next four clock cycles, write a logic 0 to WDE. This disables the
Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algo-
rithm described above. See “Timed Sequences for Changing the Configuration of the
Watchdog Timer” on page 43.
In safety level 1, WDE is overridden by WDRF in MCUSR. See “MCU Status Register –
MCUSR” on page 37 for description of WDRF. This means that WDE is always set when
WDRF is set. To clear WDE, WDRF must be cleared before disabling the Watchdog
with the procedure described above. This feature ensures multiple resets during condi-
tions causing failure, and a safe start-up after the failure.
Warning:If the watchdog timer is not be used in the application, it is important to go through a
watchdog disable procedure in the initialization of the device. If the Watchdog is acciden-
tally enabled, for example by a runaway pointer or brown-out condition, the device will be
reset, which in turn will lead to a new watchdog reset. To avoid this situation, the applica-
tion software should always clear the WDRF flag and the WDE control bit in the
initialization routine.
• Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer
is enabled. The different prescaling values and their corresponding Timeout Periods are
shown in Table 21 on page 41.




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