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ATTINY2313 Datasheet(PDF) 39 Page - ATMEL Corporation

Part No. ATTINY2313
Description  8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash
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Maker  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
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39
ATtiny2313/V
2543C–AVR–12/03
Figure 20. Watchdog Timer
Watchdog Timer Control
Register – WDTCR
• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is
configured for interrupt. WDIF is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag.
When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is
executed.
• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable
When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set,
the Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is
executed instead of a reset if a timeout in the Watchdog Timer occurs.
If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This
is useful for keeping the Watchdog Reset security while using the interrupt. After the
WDIE bit is cleared, the next time-out will generate a reset. To avoid the Watchdog
Reset, WDIE must be set after each interrupt.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog
will not be disabled. Once written to one, hardware will clear this bit after four clock
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This
MCU RESET
WATCHDOG
PRESCALER
128 kHz
OSCILLATOR
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
Bit
765
43
21
0
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
WDTCR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
X
0
0
0
Table 20. Watchdog Timer Configuration
WDE
WDIE
Watchdog Timer State
Action on Time-out
0
0
Stopped
None
0
1
Running
Interrupt
1
0
Running
Reset
1
1
Running
Interrupt




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