OBSOLETE

SCANPSC100F

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SNOS134D – SEPTEMBER 1998 – REVISED APRIL 2013

Timing Waveforms (Continued)

Figure 8. Read/Write or Write/Read (best case timing)

Figure 9. Read/Write or Write/Read (worst case timing)

(1)

This diagram shows the timing for a read followed by a write (or write followed by a read). Separate Read and Write

data/address latches and control logic allow consecutive read/write or write/read operations to be overlapped (i.e., do

not need to wait 2 or 3 SCK cycles between bus cycles). For the best case timing scenario (Figure 8: rising edge of

included after each back to back read/write or write/read sequence.

(2)

Figure 6, Figure 7, Figure 8, and Figure 9 assume that the PSC100 register participating in the bus cycle is ready to

accept/provide data. For bus cycles involving a PSC100 shifter/buffer(s), the ready status of a shifter/buffer can be

checked using the status bits in Mode Register 2 prior to the start of the bus cycle. Polling is required when the RDY

pin is not used to provide a processor “handshake”.

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