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S3C4530A Datasheet(PDF) 17 Page - Samsung semiconductor

Part No. S3C4530A
Description  16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
Download  432 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S3C4530A Datasheet(HTML) 17 Page - Samsung semiconductor

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S3C4530A
PRODUCT OVERVIEW
1-17
Table 1-3. S3C4530A PAD Type
Pad
Type
I/O
Type
Current
Drive
Cell Type
Feature
Slew-Rate
Control
ptic
I
-
LVCMOS Level
5V-tolerant
-
ptis
I
-
LVCMOS Schmit Trigger Level
5V-tolerant
-
pticu
I
-
LVCMOS Level
5V-tolerant
Pull-up register
-
pticd
I
-
LVCMOS Level
5V-tolerant
Pull-down register
-
pia_bb
I
-
Analog input with separate bulk bias -
-
pob1
O
1mA
Normal Buffer
-
-
ptot2
O
2mA
Tri-state Buffer
5V-tolerant
-
pob4
O
4mA
Normal Buffer
-
-
ptot4
O
4mA
Tri-state Buffer
5V-tolerant
-
ptot6
O
6mA
Tri-state Buffer
5V-tolerant
-
ptbsut1
I/O
1mA
LVCMOS Schmit trigger level Tri-
state Buffer
5V-tolerant Pull-up
register
-
ptbcut4
I/O
4mA
LVCMOS Level Tri-state Buffer
5V-tolerant
Medium
ptbcd4
I/O
4mA
LVCMOS Level Open drain Buffer
5V-tolerant
-
ptbst4sm
I/O
4mA
LVCMOS Schmit trigger level
5V-tolerant
Medium
ptbsut6
I/O
6mA
LVCMOS Schmit trigger level
5V-tolerant
pull-up register
-
NOTE: pticu and pticd provides 100K Ohm Pull-up(down) register. For detail information about the pad type,
see Chapter 4. Input/Output Cells of the "STD90/MDL90 0.35um 3.3V Standard Cell Library Data Book",
produced by Samsung Electronics Co., Ltd, ASIC Team
64*fMCLK
512*fMCLK
nRESET
nRSCO
NOTE: After the falling edge of nRESET, the S3C4530A count 64 cycles for a system reset
and needs further 512 cycles for a TAG RAM clear of cache.
After these cycles, the S3C4530A asserts nRCS0 when the nRESET is released.
Figure 1-3. Reset Timing Diagram


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