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S3C4530A Datasheet(PDF) 90 Page - Samsung semiconductor |
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S3C4530A Datasheet(HTML) 90 Page - Samsung semiconductor |
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90 / 432 page 
INSTRUCTION SET S3C4530A 3-48 DATA ABORTS If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH. This can happen on either the read or the write cycle (or both), and in either case, the data abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. INSTRUCTION CYCLE TIMES Swap instructions take 1S + 2N +1I incremental cycles to execute, where S, N and I are defined as squential (S- cycle), non-sequential, and internal (I-cycle), respectively. ASSEMBLER SYNTAX <SWP>{cond}{B} Rd,Rm,[Rn] { cond} Two-character condition mnemonic. See Table 3-2. { B} If B is present then byte transfer, otherwise word transfer Rd,Rm,Rn Expressions evaluating to valid register numbers Examples SWP R0,R1,[R2] ; Load R0 with the word addressed by R2, and ; store R1 at R2. SWPB R2,R3,[R4] ; Load R2 with the byte addressed by R4, and ; store bits 0 to 7 of R3 at R4. SWPEQ R0,R0,[R1] ; Conditionally swap the contents of the ; word addressed by R1 with R0. |
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