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S3C4530A Datasheet(PDF) 74 Page - Samsung semiconductor

Part No. S3C4530A
Description  16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
Download  432 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S3C4530A Datasheet(HTML) 74 Page - Samsung semiconductor

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INSTRUCTION SET
S3C4530A
3-32
ASSEMBLER SYNTAX
<LDR|STR>{cond}{B}{T} Rd,<Address>
where:
LDR
Load from memory into a register
STR
Store from a register into memory
{
cond}
Two-character condition mnemonic. See Table 3-2.
{
B}
If B is present then byte transfer, otherwise word transfer
{
T}
If T is present the W bit will be set in a post-indexed instruction, forcing non-
privileged mode for the transfer cycle. T is not allowed when a pre-indexed
addressing mode is specified or implied.
Rd
An expression evaluating to a valid register number.
Rn and Rm
Expressions evaluating to a register number. If Rn is R15 then the assembler will
subtract 8 from the offset value to allow for ARM7TDMI pipelining. In this case base
write-back should not be specified.
<Address>can be:
1
An expression which generates an address:
The assembler will attempt to generate an instruction using the PC as a base and a
corrected immediate offset to address the location given by evaluating the
expression. This will be a PC relative, pre-indexed address. If the address is out of
range, an error will be generated.
2
A pre-indexed addressing specification:
[Rn]
offset of zero
[Rn,<#expression>]{!}
offset of <expression> bytes
[Rn,{+/-}Rm{,<shift>}]{!}
offset of +/- contents of index register,
shifted by <shift>
3
A post-indexed addressing specification:
[Rn],<#expression>
offset of <expression> bytes
[Rn],{+/-}Rm{,<shift>}
offset of +/- contents of index register,
shifted as by <shift>.
<shift>
General shift operation (see data processing instructions) but you cannot specify
the shift amount by a register.
{
!}
Writes back the base register (set the W bit) if! is present.


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