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S3C4530A Datasheet(PDF) 65 Page - Samsung semiconductor

Part No. S3C4530A
Description  16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
Download  432 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S3C4530A Datasheet(HTML) 65 Page - Samsung semiconductor

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S3C4530A
INSTRUCTION SET
3-23
MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The
instruction encoding is shown in Figure 3-12.
The multiply and multiply-accumulate instructions use an 8 bit Booth's algorithm to perform integer multiplication.
31
27
19
15
Cond
28
16
11
12
21 20
S
Rd
Rn
[15:12][11:8][3:0] Operand Registers
[19:16] Destination Register
[20] Set Condition Code
0 = Do not alter condition codes
1 = Set condition codes
[21] Accumulate
0 = Multiply only
1 = Multiply and accumulate
[31:28] Condition Field
22
1 0 0 1
Rs
Rm
A
0
0
0 0 0 0
8 7
4 3
0
Figure 3-12. Multiply Instructions
The multiply form of the instruction gives Rd: = Rm * Rs. Rn is ignored, and should be set to zero for
compatibility with possible future upgrades to the instruction set. The multiply-accumulate form gives Rd: = Rm *
Rs + Rn, which can save an explicit ADD instruction in some circumstances. Both forms of the instruction work
on operands which may be considered as signed (2’ complement) or unsigned integers.
The results of a signed multiply nd of an unsigned multiply of 32 bit operands differ only in the upper 32 bits-the
low 32 bits of the signed and unsigned results are identical. As these instructions only produce the low 32 bits of a
multiply, they can be used for both signed and unsigned multiplies.
For example consider the multiplication of the operands:
Operand A
Operand B
Result
0xFFFFFFF6
0x0000001
0xFFFFFF38
If the Operands are Interpreted as Signed
Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as
0xFFFFFF38.
If the Operands are Interpreted as Unsigned
Operand A has the value 4294967286, operand B has the value 20 and the result is 85899345720, which is
represented as 0x13FFFFFF38, so the least significant 32 bits are 0xFFFFFF38.
Operand Restrictions
The destination register Rd must not be the same as the operand register Rm. R15 must not be used as an
operand or as the destination register.
All other register combinations will give correct results, and Rd, Rn and Rs may use the same register when
required.


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