 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
S3C4530A Datasheet(PDF) 43 Page - Samsung semiconductor |
|
||||||||||||||||||||||||||||||
S3C4530A Datasheet(HTML) 43 Page - Samsung semiconductor |
|
|
43 / 432 page 
S3C4530A INSTRUCTION SET 3-1 3 INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set and the THUMB instruction set in the ARM7TDMI core. FORMAT SUMMARY The ARM instruction set formats are shown below. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data processing/ PSR Transfer Multiply Multiply Long Single data swap Branch and exchange Halfword data transfer: register offset Halfword data transfer: immediate offset Block data transfer Branch Coprocessor data transfer Coprocessor data Operation Coprocessor register Transfer Software Interrupt Undefined Single data transfer Cond 1 1 1 1 Ignored by processor Cond 1 1 1 0 CRn Rd CP Opc L CP# CP# 1 CRm Cond 1 1 1 0 CRn CRd CP Opc CP# CP# 0 CRm Cond 1 1 0 P U N W L Rn CRd CP# Offset Cond 1 0 1 L Offset Cond 1 0 0 P U S W L Rn Register List Cond 0 1 1 1 Cond 0 1 1 P U B W L Rn Rd Offset Cond 0 0 0 P U 1 W L Rn Rd Offset 1 S H 1 Offset Cond 0 0 0 P U 0 W L Rn Rd 0 0 0 0 1 S H 1 Rm Cond 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rn Cond 0 0 0 1 0 B 0 0 Rn Rd Rm 0 0 0 0 1 0 0 1 Cond 0 0 0 0 1 U A S RdHi RnLo Rn 1 0 0 1 Rm Cond 0 0 0 0 0 0 A S Rd Rn Rs 1 0 0 1 Rm Cond 0 0 1 Opcode S Rn Rd Operand2 Figure 3-1. ARM Instruction Set Format NOTE Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations. |
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
