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DRV10963 Datasheet(PDF) 17 Page - Texas Instruments

Part No. DRV10963
Description  DRV10963 5-V, Three-Phase, Sensorless BLDC Motor Driver
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DRV10963 Datasheet(HTML) 17 Page - Texas Instruments

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DRV10963
www.ti.com
SLAS955A – MARCH 2013 – REVISED JULY 2015
any of the DRV10963Jx parts then the DRV10963P part can be used. The DRV10963P part provides blank OTP
settings that can be configured for optimal performance in your application. The TI provided EVM and GUI will
allow you to configure the OTP settings. Consult your TI representative if your application requires settings that
are not available in the DRV10963Jx configurations described and if you are unable to use the DRV10963P
option. The OTP bits used to configure the various part revisions are shown for reference in Table 10.
Table 9. OTP Configuration Bits
OTP BIT NAMES
DESCRIPTION
REFERENCE TO
Minimum
MINOP_DC[1:0]
operational duty
Figure 6
cycle
Standby Mode and Sleep
SLEEP_EN
Sleep mode enable
Mode
Start-up time and
TARA_TH[3:0]
Spin up Settings
accelerate setting
Openloop to closed
HO_TH[3:0]
Spin up Settings
loop threshold.
Current limit
ILIMIT[2:0]
Table 7
setting.
Control advance
CTRL_ANG[4:0]
Table 8
angle.
Motor Frequency Feedback
FGOPT
FG output option.
(FG)
Table 10. The OTP Setting of the Factory Configured Parts
MINOP_DC
CTRL_ANG
SLEEP_EN
TARA_TH [3:0]
HO_TH [3:0]
ILIMIT [2:0]
FGOPT
[1:0]
[4:0]
DRV10963JJ
2
1
7
8
4
6
0
DRV10963JM
2
1
E
4
4
6
1
DRV10963JU
2
1
C
7
4
6
0
DRV10963JA
2
1
7
8
4
8
0
DRV10963P
0
0
0
0
0
0
0
7.4 Device Functional Modes
7.4.1 Standby Mode and Sleep Mode
When the PWM commanded duty cycle input is lower than 1.5%, the phase outputs will be put into a high
impedance state. The device will stop driving the motor. The device logic is still active during standby mode and
the DRV10963 device will consume current as specified by IVCC.
When the PWM commanded duty cycle input is driven to 0% (less than VIL_PWM for at least TSLEEP time), the
DRV10963 device will enter a low power sleep mode. In sleep mode, most of the circuitry in the device will be
disabled to minimize the system current. The current consumption in this state is specified by IVCC_SLEEP.
The device will remain in sleep mode until either the PWM commanded duty cycle input is driven to a logic high
(higher than VIH_PWM) or the PWM input pin is allowed to float. If the input is allowed to float an internal pullup
resistor will raise the voltage to a logic high level.
Recovering from sleep mode is treated the same as power on condition as illustrated in Figure 7.
As part of the device initialization the motor resistance value and the motor Kt value are measured during the
initial motor spin up as shown in Figure 7. Whenever the part is executing the initialization sequence it is
important to note that the values determined by any previous spin up cycles no longer exist. In order for the
motor resistance value and the motor Kt value to be properly initialized the system should be allowed to come to
a complete stop before the next restart attempt.
Copyright © 2013–2015, Texas Instruments Incorporated
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