DRV10963_15 datasheet(8/31 Pages) TI | DRV10963 5-V, Three-Phase, Sensorless BLDC Motor Driver

8 / 31 page

100% output

Vph

VCC

VCC*PWMdc

DRV10963

SLAS955A – MARCH 2013 – REVISED JULY 2015

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7.3 Feature Description

7.3.1 Speed Input and Control

The DRV10963 provides 3-phase 25-kHz PWM outputs which have an average value of sinusoidal waveforms

from phase to phase. When any phase is measured with reference to ground, the waveform observed will be a

PWM encoded sinusoid coupled with 3rd order harmonics as shown in Figure 2. This encoding scheme simplifies

the driver requirements because there will always be one phase output that is equal to zero.

Figure 2. Sinusoidal Phase Encoding Used in DRV10963

The output amplitude is determined by the supply voltage (VCC) and the commanded PWM duty cycle (PWM) as

described in Equation 1 and illustrated in Figure 3. The maximum amplitude is applied when the commanded

PWM duty cycle is 100%.

Vphpk = PWMdc × VCC

(1)

Figure 3. Output Voltage Amplitude Adjustment

The motor speed is controlled indirectly by using the PWM command to control the amplitude of the phase

voltages which are applied to the motor.

The duty cycle of PWM input is converted into a 9 bit digital number (from 0 to 511). The control resolution is

1/512

≈ 0.2%. The duty cycle analyzer implements a first order transfer function between the input duty cycle and

the 9 bits digital number. This is illustrated in Figure 4, where

τ=80 ms.

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