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ADN8833 Datasheet(PDF) 20 Page - Analog Devices |
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ADN8833 Datasheet(HTML) 20 Page - Analog Devices |
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20 / 23 page  ADN8833 Data Sheet Rev. A | Page 20 of 23 PCB LAYOUT GUIDELINES TEMPERATURE SIGNAL CONDITIONING TEC VOLTAGE LIMITING TEC CURRENT LIMITING TEC VOLTAGE SENSING TEC CURRENT SENSING TEC DRIVER OBJECT THERMOELECTRIC COOLER (TEC) TEMPERATURE ERROR COMPENSATION TEMPERATURE SENSOR SOURCE OF ELECTRICAL POWER TARGET TEMPERATURE Figure 34. System Block Diagram BLOCK DIAGRAMS AND SIGNAL FLOW The ADN8833 integrates analog signal conditioning blocks, a load protection block, and a TEC driver power stage all in a single IC. To achieve the best possible circuit performance, attention must be paid to keep noise of the power stage from contaminating the sensitive analog conditioning and protection circuits. In addition, the layout of the power stage must be performed such that the IR losses are minimized to obtain the best possible electrical efficiency. The system block diagram of the ADN8833 is shown in Figure 34. GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS Each printed circuit board (PCB) layout is unique because of the physical constraints defined by the mechanical aspects of a given design. In addition, several other circuits work in conjunction with the TEC driver; these circuits have their own layout requirements, so there are always compromises that must be made for a given system. However, to minimize noise and keep power losses to a minimum during the PCB layout process, observe the following guidelines. General PCB Layout Guidelines Switching noise can interfere with other signals in the system; therefore, the switching signal traces must be placed away from the power stage to minimize the effect. If possible, place the ground plate between the small signal layer and power stage layer as a shield. Supply voltage drop on traces is also an important consideration because it determines the voltage headroom of the TEC driver at high currents. For example, if the supply voltage from the front-end system is 3.3 V, and the voltage drop on the traces is 0.5 V, PVIN sees only 2.8 V, which limits the maximum voltage of the linear regulator as well as the maximum voltage across the TEC. To mitigate the voltage waste on traces and impedance interconnection, place the ADN8833 and the input decoupling components close to the supply voltage terminal. This placement not only improves the system efficiency, but also provides better regulation performance at the output. To prevent noise signal from circulating through ground plates, reference all of the sensitive analog signals to AGND and connect AGND to PGNDS using only a single point connection. This ensures that the switching currents of the power stage do not flow into the sensitive AGND node. PWM Power Stage Layout Guidelines The PWM power stage consists of a MOSFET pair that forms a switch mode output that switches current from PVIN to the load via an LC filter. The ripple voltage on the PVIN pin is caused by the discontinuous current switched by the PWM side MOSFETs. This rapid switching causes voltage ripple to form at the PVIN input, which must be filtered using a bypass capacitor. Place a 10 μF capacitor as close as possible to the PVIN pin to connect PVIN to PGNDS. Because the 10 μF capacitor is sometimes bulky and has higher ESR and ESL, a 100 nF decoupling capacitor is usually used in parallel with it, placed between PVIN and PGNDS. Because the decoupling is part of the pulsating current loop, which carries high di/dt signals, the traces must be short and wide to minimize the parasitic inductance. As a result, this capacitor is usually placed on the same side of the board as the ADN8833 to ensure short connections. If the layout requires that 10 μF capacitor be on the opposite side of the PCB, use multiple vias to reduce via impedance. The layout around the SW node is also critical because it switches between PVIN and ground rapidly, which makes this node a strong EMI source. Keep the copper area that connects the SW node to the inductor small to minimize parasitic capacitance between the SW node and other signal traces. This helps minimize noise on the SW node due to excessive charge injection. However, in high current applications, the copper area may be increased reasonably to provide heat sink and to sustain high current flow. Connect the ground side of the capacitor in the LC filter as close as possible to PGNDS to minimize the ESL in the return path. |
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Similar Description - ADN8833 |
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