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ISL78229ARZ Datasheet(PDF) 4 Page - Intersil Corporation |
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ISL78229ARZ Datasheet(HTML) 4 Page - Intersil Corporation |
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4 / 71 page  ISL78229 4 FN8656.3 February 12, 2016 Submit Document Feedback IMON 5 IMON is the average current monitor pin for the sum of the two phases’ inductor currents. It is used for average current limiting and average current protection functions. The sourcing current from the IMON pin is the sum of the two CSA’s outputs plus a fixed 17µA offset current. With each CSA sensing individual phase’s inductor current, the IMON signal represents the sum of the two phases’ inductor currents and it is the input current for the boost. A resistor in parallel with a capacitor are needed to be placed from IMON to ground. The IMON pin output current signal builds up the average voltage signal representing the average current sense signals. A constant average current limiting function and an average current protection are implemented based on the IMON signal. 1. Constant Average Current Limiting: A Constant Current (CC) control loop is implemented to limit the IMON average current signal using a 1.6V reference, which ultimately limits the total input average current to a constant level. 2. Average Current Protection: If the IMON pin voltage is higher than 2V, the part will go into either Hiccup or Latch-off fault protection as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35. Refer to “Average Current Sense for 2 Phases - IMON” on page 32 for more details. TRACK 6 External reference input pin for the IC output voltage regulation loop to follow. The input reference signal can be either digital or analog signal selected by the ATRK/DTRK pin configuration. If the TRACK function is not used, connect the TRACK pin to VCC and the internal VREF_DAC will work as the reference. Refer to “Digital/Analog TRACK Function” on page 26 for more details. ADDR1 7 ADDR1, a logic input in combination with ADDR2, selects one of four bus addresses. Refer to “Device Identification Address and Read/Write” on page 42 for more details. ADDR2 8 ADDR2, a logic input in combination with ADDR1, selects one of four bus addresses. Refer to “Device Identification Address and Read/Write” on page 42 for more details. PGOOD 9 Provides an open-drain power-good signal. Pull up this pin with a resistor to this IC’s VCC for proper function. When the output voltage is within OV/UV thresholds and soft-start is completed, the internal PGOOD open-drain transistor is open and PGOOD is pulled HIGH. It will be pulled low once output UV/OV or input OV conditions are detected. Refer to “PGOOD Signal” on page 31 for more details. FSYNC 10 A dual-function pin for switching frequency setting and synchronization defined as follows: 1. The PWM switching frequency can be programmed by a resistor RFSYNC from this pin to ground. The PWM frequency refers to a single-phase switching frequency in this datasheet. The typical programmable frequency range is 50kHz to 1.1MHz. 2. The PWM switching frequency can also be synchronized to an external clock applied on the FSYNC pin. The FSYNC pin detects the input clock signal’s rising edge to be synchronized with. The typical detectable minimum pulse width of the input clock is 20ns. The rising edge of LG1 is delayed by 35ns from the rising edge of the input clock signal at the FSYNC pin. Once the internal clock is locked to the external clock, it will latch to the external clock. If the external clock on the FSYNC pin is removed, the switching frequency oscillator will shut down. The part will then detect PLL_LOCK fault and go to either Hiccup mode or Latch-off mode as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35. If the part is set in Hiccup mode, the part will restart with the frequency set by RFSYNC. SGND 11 Signal ground pin that the internal sensitive analog circuits refer to. Connect this pin to large copper ground plane free from large noisy signals. In layout power flow planning, avoid having the noisy high frequency pulse current flowing through the ground area around the IC. SDA 12 Serial bus data Input/Output. Requires pull-up. SCL 13 Serial bus clock Input. Requires pull-up. SALERT 14 PMBus™ Alert Output. An open-drain output that is pulled low when a fault condition is detected. Requires pull-up. Refer to “Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34 for more details. NTC 15 External temperature sensor input. An NTC resistor from this pin to GND can be used as the external temperature sensing component. A 20µA current sources out of this pin. The voltage at this pin is 20µA times the NTC resistor, which represents the temperature. The voltage on this pin is converted by the internal ADC and stored in the NTC register which can be read over the PMBus™. Refer to “External Temperature Monitoring and Protection (NTC Pin)” on page 38 for more details. DE/PHDRP 16 This pin is used to select Diode Emulation mode (DE), Phase Dropping (PH_DROP) mode or continuous conduction mode (CCM). There are 3 configurable modes: 1. DE mode; 2. DE plus PH_DROP mode; 3. CCM mode. Refer to Table 2 on page 34 for the 3 configurable options. The phase dropping mode is not allowed with external synchronization. RBLANK 17 A resistor from this pin to ground programs the blanking time for current sensing after the PWM is ON (LG is ON). This blanking time is also termed as tMINON time meaning minimum ON-time once a PWM pulse is ON. Refer to “Minimum On-Time (Blank Time) Consideration” on page 29 for the selection of RBLANK. Functional Pin Description (Continued) PIN NAME PIN # DESCRIPTION |
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