2

SCD5958 Rev A 3/6/14

Aeroflex Plainview

Gain compression will occur near either power supply extremes but can be avoided if the references are more

than 200mV away from the respective supply terminals. The input span can be less than 4 volts at the expense of

ultimate resolution

The analog channels input impedance is primary capacitance (20pF typical). The input voltage charges a

track-and-hold hold capacitor through transmission gates. The input bandwidth is determined by the slew rate of

the hold amplifier and is adequate to allow input sampling in three clock periods (3uS nominal). The ultimate

bandwidth is determined by the aperture uncertainty associated with the closing of the sample gate

(approximately 5nS). The converter bandwidth is then determined by the sampling Nyquist frequency rather than

the input signal; change rate (dv/dt) and the LSB weight in volts as would be the case if there were no sample and

hold.

Start-Convert (STCNV_H), Busy (BUSY_L) and End-Of-Convert (EOC_H) status and control line are provided.

The converter will operate in either continuous or single conversion modes. To operate in continuous mode,

STCNV_H should be tied to BUSY_L. The digital output register changes at the end of a conversion and is

available when EOC_H is asserted High. The output circuitry operates from a voltage independent of the

remainder of the chip such that I/O is compatible with digital systems from, less than 3.3 volts, to 5 volts.

The converter divides the reference voltage into 16 segments with a linear weighted resistor network. The voltage

on any segment is passed to a linear 10-bit DAC for interpolation. The architecture is inherently capable of

monotonic operation. Typically INL is 0.12% FSR and DNL is < 0.03% FSR. The sampled input voltage is

compared to the output of the two stage DAC for a 14-bit successive approximation conversion.

+0.4 and GND-0.4 to avoid forward biasing protection paths.

application dependent.

Notes:

- The STCNV_H is a dynamic input (positive edge triggered) and should not be tied to a static voltage.

- The input signals should be low pass filtered to reduce high frequency noise

- If Sleep mode is enabled (EN_H=0), when waking up (EN_H=1), the unit has to complete an entire

conversion cycle so the digital logic is in the proper state.

Ex. If using a 1MHz clock; after EN_H=1 and 20us after STCNV_H is applied.