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LM4546A Datasheet(PDF) 5 Page - Texas Instruments |
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LM4546A Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 32 page  OBSOLETE LM4546A www.ti.com SNOS991E – NOVEMBER 2002 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (1)(2) (continued) The following specifications apply for AVDD = 5V, DVDD = 5V, Sampling Frequency (Fs) = 48 kHz, single codec configuration, unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified. LM4546A Units Symbol Parameter Conditions (Limits) Typical(3) Limit(4) 0.20 x VOL Low level output voltage V (max) DVDD IL Input Leakage Current AC Link inputs ±10 µA IL Tri state Leakage Current High impedance AC Link outputs ±10 µA IDR Output drive current AC Link outputs 5 mA Digital Timing Specifications(7) FBC BIT_CLK frequency 12.288 MHz TBCP BIT_CLK period 81.4 ns TCH BIT_CLK high Variation of BIT_CLK duty cycle from 50% ±20 % (max) FSYNC SYNC frequency 48 kHz TSP SYNC period 20.8 µs TSH SYNC high pulse width 1.3 µs TSL SYNC low pulse width 19.5 µs TDSETUP Setup Time for codec data input SDATA_OUT to falling edge of BIT_CLK 15 ns (min) Hold time of SDATA_OUT from falling edge TDHOLD Hold Time for codec data input 5 ns (min) of BIT_CLK TSSETUP Setup Time for codec SYNC input SYNC to rising edge of BIT_CLK TBD ns (min) Hold time of SYNC from rising edge of TSHOLD Hold Time for codec SYNC input TBD ns (min) BIT_CLK Output Delay of SDATA_IN from rising TCO Output Valid Delay TBD 15 ns (max) edge of BIT_CLK BIT_CLK, SYNC, SDATA_IN or TRISE Rise Time 6 ns (max) SDATA_OUT BIT_CLK, SYNC, SDATA_IN or TFALL Fall Time 6 ns (max) SDATA_OUT TRST_LOW RESET# active low pulse width For Cold Reset 1.0 µs (min) TRST2CLK RESET# inactive to BIT_CLK start up For Cold Reset TBD 162.8 ns (min) TSH SYNC active high pulse width For Warm Reset 1.3 TBD µs (min) TSYNC2CLK SYNC inactive to BIT_CLK start up For Warm Reset TBD 162.8 ns (min) Delay from end of Slot 2 to BIT_CLK, TS2_PDOWN AC Link Power Down Delay 1 µs (max) SDATA_IN low Time from minimum valid supply levels to TSUPPLY2RST Power On Reset 1 µs (min) end of Reset TSU2RST Setup to trailing edge of RESET# For ATE Test Mode 15 ns (min) TRST2HZ Rising edge of RESET# to Hi-Z For ATE Test Mode 25 ns (max) Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM4546A |
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