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SC4809BIMSTR Datasheet(PDF) 5 Page - Semtech Corporation |
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SC4809BIMSTR Datasheet(HTML) 5 Page - Semtech Corporation |
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5 / 16 page  5 2005 Semtech Corp. www.semtech.com SC4809A/B/C POWER MANAGEMENT Pin Descriptions FB: This pin is the summing node for current sense feed- back, voltage sense feedback (by optocoupler) and slope compensation. Slope compensation is derived from the rising voltage at the time capacitor and can be buffered with an external small signal NPN transistor. External high frequency filter capacitance applied from this node to GND is discharged by an internal 250 Ω on-resistance NMOS FET during PWM off -time and offers effective lead- ing edge blanking set by the RC time constant of the feedback resistance from the current sense resistor to the FB input and the high frequency filter capacitor ca- pacitance at this node to GND. GND: Reference ground and power ground for all func- tions. OUT: This pin is the logic level drive output to the exter- nal MOSFET driver circuit (similar to SC1301). VREF: The internal 4V (A) / 5V (B & C) reference output. This reference is buffered and is available on the VREF pin. VREF should be bypassed with a 0.47 - 1.0µF ce- ramic capacitor. RCT: The oscillator frequency is configured by connect- ing resistor RT from VREF to RCT and capacitor CT from RCT to ground. Using the equation below values for RT and CT can be selected to provide the desired OUT fre- quency. − • • − = − REF K P V V 1 ln CT RT 1 F where V P-K = RCT peak voltage DMAX: Duty cycle up to 98% can be programmed via R4 and R5 (the resistor divider from Vref in the Application Circuit). When DMAX pin is taken above 3V, 100% duty cycle is achieved. SS: This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 8µA current source. Under normal soft start SS is dis- charged to less than 1V and then ramps positive to 1V during which time the output driver is held low. As SS charges from 1V to 2V, soft start is implemented by an increasing output duty cycle. If SS is taken below shut- down threshold, the output driver is inhibited and held low. The user accessible voltage reference also goes low and IDD < 100µA. VDD: The power input connection for this device. This pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1µF ceramic capacitor. LUVLO: Line undervoltage lock out pin. An external resis- tive divider will program the undervoltage lock out level. During the LUVLO, the Driver outputs are disabled and the softstart is reset. SYNC: SYNC is a positive edge triggered input with a threshold set to 2.1V. In the Bi-Phase operation mode the SYNC pin should be connected to the CT (Timing Capacitor) of the second controller. This will force a out of phase operation. In a single controller opera- tion, SYNC could be grounded or connected to an exter- nal synchronization clock with a frequency higher than the on-board oscillator frequency. The external OSC fre- quency should be 30% greater for guaranteed SYNC operation. |
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