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54F533DM Datasheet(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. 54F533DM
Description  Octal Transparent Latch with TRI-STATE Outputs
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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54F533DM Datasheet(HTML) 2 Page - National Semiconductor (TI)

   
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Unit LoadingFan Out
54F74F
Pin Names
Description
UL
Input IIH IIL
HIGHLOW
Output IOH IOL
D0–D7
Data Inputs
1010
20 mA b06 mA
LE
Latch Enable Input (Active HIGH)
1010
20 mA b06 mA
OE
Output Enable Input (Active LOW)
1010
20 mA b06 mA
O0–O7
Complementary TRI-STATE Outputs
15040 (333)
b
3 mA24 mA (20 mA)
Function Table
Inputs
Output
LE
OE
DO
HL
H
L
HL
L
H
LL
X
O0
XH
X
Z
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Functional Description
The ’F533 contains eight D-type latches with TRI-STATE
output buffers When the Latch Enable (LE) input is HIGH
data on the Dn inputs enters the latches In this condition
the latches are transparent ie a latch output will change
state each time its D input changes When LE is LOW the
latches store the information that was present on the D in-
puts a setup time preceding the HIGH-to-LOW transition of
LE The TRI-STATE buffers are controlled by the Output
Enable (OE) input When OE is LOW the buffers are in the
bi-state mode When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches
Logic Diagram
TLF9548 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


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