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54F402FM Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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54F402FM Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 12 page Unit LoadingFan Out 54F74F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL S0–S3 Polynomial Select Inputs 10067 20 mA b04 mA CWG Check Word Generate Input 10067 20 mA b04 mA DCW Serial DataCheck Word 285(100)133(67) b 57 mA(b2 mA)8 mA (4 mA) D Data Input 10067 20 mA b04 mA ER Error Output 267(133) 16 mA (8 mA) RO Register Output 285(100)133(67) b 57 mA(b2 mA)8 mA (4 mA) CP Clock Pulse 10067 20 mA b04 mA SEI Serial Expansion Input 10067 20 mA b04 mA RFB Register Feedback 10067 20 mA b04 mA MR Master Reset 10067 20 mA b04 mA P Preset 10067 20 mA b04 mA Open Collector Functional Description The ’F402 Serial Data Polynomial GeneratorChecker is an expandable 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic For encoding the data stream (message polynomial) is divided by a selected polynomial This divi- sion results in a remainder (or residue) which is appended to the message as check bits For error checking the bit stream containing both data and check bits is divided by the same selected polynomial If there are no detectable errors this division results in a zero remainder Although it is possi- ble to choose many generating polynomials of a given de- gree standards exist that specify a small number of useful polynomials The ’F402 implements the polynomials listed in Table I by applying the appropriate logic levels to the select pins S0 S1 S2 and S3 The ’F402 consists of a 16-bit register a Read Only Memory (ROM) and associated control circuitry as shown in the Block Diagram The polynomial control code presented at inputs S0 S1 S2 and S3 is decoded by the ROM selecting the desired polynomial or part of a polynomial by establish- ing shift mode operation on the register with Exclusive OR (XOR) gates at appropriate inputs To generate the check bits the data stream is entered via the Data Inputs (D) us- ing the LOW-to-HIGH transition of the Clock Input (CP) This data is gated with the most significant Register Output (RO) via the Register Feedback Input (RFB) and controls the XOR gates The Check Word Generate (CWG) must be held HIGH while the data is being entered After the last data bit is entered the CWG is brought LOW and the check bits are shifted out of the register(s) and appended to the data bits (no external gating is needed) To check an incoming message for errors both the data and check bits are entered through the D Input with the CWG Input held HIGH The Error Output becomes valid af- ter the last check bit has been entered into the ’F402 by a LOW-to-HIGH transition of CP with the exception of the Ethernet polynomial (see Applications paragraph) If no de- tectable errors have occurred during the data transmission the resultant internal register bits are all LOW and the Error Output (ER) is HIGH If a detectable error has occurred ER is LOW ER remains valid until the next LOW-to-HIGH tran- sition of CP or until the device has been preset or reset A HIGH on the Master Reset Input (MR) asynchronously clears the entire register A LOW on the Preset Input (P) asynchronously sets the entire register with the exception of 1 The Ethernet residue selection in which the registers containing the non-zero residue are cleared 2 The 56th order polynomial in which the 8 least significant register bits of the least significant device are cleared and 3 Register Se0 in which all bits are cleared 2 |
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