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JHB320240DSBRCGNUA Datasheet(PDF) 7 Page - Jewel Hill Electronic |
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JHB320240DSBRCGNUA Datasheet(HTML) 7 Page - Jewel Hill Electronic |
7 / 26 page JHB320240D VER: 5.01 - 6 - Issue date: 2013/08/01 JEWEL HILL ELECTRONIC CO.,LTD. 7. MODULE FUNCTION DESCRIPTION 7.1. PIN DESCRIPTION Pin No. Symbol Description 1 NC No connect 2 NC No connect 3 DB0 Data Bit 0 4 DB1 Data Bit1 5 DB2 Data Bit2 6 DB3 Data Bit3 7 /DISPOFF During the LOW period of this signal, V0 is selected as SC0-SC80’S Outputs and the display is therefore turned off. 8 FLM Frame Start Signal 9 NC No Connect 10 CL1 In SEGMENT driver application mode,the 80-bits display data is latched into the shift register at the falling edge of this clock. In COMMON driver application mode, CL1 is used as shifting clock of COMMON output data 11 CL2 In SEGMENT driver application mode,CL2 is the shifting clock of 20X4-bit bi-directional shift register. 12 VDD Power Supply for Positive (+5V) 13 VSS Power Supply for Ground 14 VEE Negative Voltage for LCD Power Supply 15 VO Contrast Adjustment Voltage 16 FGND Frame Ground |
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Similar Description - JHB320240DSBRCGNUA |
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