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DRV83055PHP Datasheet(PDF) 9 Page - Texas Instruments |
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DRV83055PHP Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 59 page  9 DRV8305 www.ti.com SLVSCX2B – AUGUST 2015 – REVISED FEBRUARY 2016 Product Folder Links: DRV8305 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Electrical Characteristics (continued) PVDD = 4.4 to 45 V, TA = 25°C, unless specified under test condition PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOW SIDE (GLA, GLB, GLC) PEAK CURRENT GATE DRIVE IDRIVEP_LS Low-side peak source current IDRIVEP_HS = 0000 0.01 A IDRIVEP_HS = 0001 0.02 IDRIVEP_HS = 0010 0.03 IDRIVEP_HS = 0011 0.04 IDRIVEP_HS = 0100 0.05 IDRIVEP_HS = 0101 0.06 IDRIVEP_HS = 0110 0.07 IDRIVEP_HS = 0111 0.125 IDRIVEP_HS = 1000 0.25 IDRIVEP_HS = 1001 0.5 IDRIVEP_HS = 1010 0.75 IDRIVEP_HS = 1011 1 IDRIVEP_HS = 1100, 1101, 1110, 1111 0.05 LOW SIDE (GLA, GLB, GLC) PEAK CURRENT GATE DRIVE IDRIVEN_LS Low-side peak sink current IDRIVEN_HS = 0000 0.02 A IDRIVEN_HS = 0001 0.03 IDRIVEN_HS = 0010 0.04 IDRIVEN_HS = 0011 0.05 IDRIVEN_HS = 0100 0.06 IDRIVEN_HS = 0101 0.07 IDRIVEN_HS = 0110 0.08 IDRIVEN_HS = 0111 0.25 IDRIVEN_HS = 1000 0.5 IDRIVEN_HS = 1001 0.75 IDRIVEN_HS = 1010 1 IDRIVEN_HS = 1011 1.25 IDRIVEN_HS = 1100, 1101, 1110, 1111 0.06 GATE PULL DOWN, MOTOR OFF STATE (BRIDGE IN HI-Z) RSLEEP_PD Gate pulldown resistance, SLEEP, undervoltage and sleep mode 2 V < PVDD < PVDD_UVLO2 GHX to GND; GLX to GND 2000 Ω RSTANDBY_PD Gate pulldown resistance, STANDBY, standby mode (Parallel with ISTANDBY_PD) PVDD > PVDD_UVLO2; EN_GATE = low; GHX to GND; GLX to GND 750 Ω IOPERATING_PD Gate pulldown current, OPERATING, operating mode PVDD > PVDD_UVLO2; EN_GATE = high; GHX to SHX; GLX to SLX 50 mA GATE PULL DOWN, MOTOR ON STATE (IDRIVE/tdrive) IHOLD Gate pulldown current, holding PVDD > PVDD_UVLO2; EN_GATE = high; GHX to SHX; GLX to SLX 50 mA IPULLDOWN Gate pulldown current, strong PVDD > PVDD_UVLO2; EN_GATE = high; GHX to SHX; GLX to SLX 1.25 A |
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