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JHT24096AHYPCANUA Datasheet(PDF) 7 Page - Jewel Hill Electronic |
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JHT24096AHYPCANUA Datasheet(HTML) 7 Page - Jewel Hill Electronic |
7 / 23 page JHG24096A VER:3.01 - 6 - Issue date: 2013/08/01 JEWEL HILL ELECTRONIC CO.,LTD. 7. MODULE FUNCTION DESCRIPTION 7.1. PIN DESCRIPTION Pin No. Symbol Description 1 NC No connect 2 BM1 3 BM0 Bus mode and interface selection terminal 4 CS Chip Selection terminal 5 RST Reset signal input terminal 6 CD Data/Command Register Selection 7 WR0 8 WR1 WR[1:0] controls the read/write operation of the host interface. 9-16 D0-D7 Bi-directional bus for both serial and parallel host interfaces. Connect unused pins to VDD or VSS. 17 VDD 18 VDD2 Power supply terminal, connect together for a positive voltage(2.7 to 3.3V) 19 VSS Ground 20 VLCD LCD power supply, A by-pass capacitor C L between VLCD and VSS 21 VB0+ 22 VB0- LCD Bias Voltages. These are the voltage source to provide SEG driving currents. These voltages are generated internally. Connect capacitors of CBX value between VB0+ and VB0–. 23 VBIAS Connect a small bypass capacitor between VBIAS and VSS to reduce noise. 24 VB1+ 25 VB1- LCD Bias Voltages. These are the voltage source to provide SEG driving currents. These voltages are generated internally. Connect capacitors of CBX value between VB1+ and VB1–. 26 NC No connect |
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