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RM48L950 Datasheet(PDF) 6 Page - Texas Instruments |
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RM48L950 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 179 page RM48L950, RM48L750, RM48L550 SPNS174C – APRIL 2012 – REVISED JUNE 2015 www.ti.com Table of Contents 1 Device Overview ......................................... 1 6.12 Parity Protection for Peripheral RAMs .............. 86 1.1 Features .............................................. 1 6.13 On-Chip SRAM Initialization and Testing ........... 88 1.2 Applications ........................................... 2 6.14 External Memory Interface (EMIF) .................. 90 1.3 Description ............................................ 3 6.15 Vectored Interrupt Manager ......................... 97 1.4 Functional Block Diagram ............................ 5 6.16 DMA Controller ..................................... 100 2 Revision History ......................................... 7 6.17 Real Time Interrupt Module ........................ 103 3 Device Comparison ..................................... 8 6.18 Error Signaling Module ............................. 105 4 Terminal Configuration and Functions ............. 9 6.19 Reset / Abort / Error Sources ...................... 109 4.1 PGE QFP Package Pinout (144-Pin) ................. 9 6.20 Digital Windowed Watchdog ....................... 111 4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array) 10 6.21 Debug Subsystem ................................. 112 4.3 Terminal Functions ................................. 11 7 Peripheral Information and Electrical Specifications ......................................... 123 5 Specifications .......................................... 44 7.1 Peripheral Legend ................................. 123 5.1 Absolute Maximum Ratings ........................ 44 7.2 Multibuffered 12-Bit Analog-to-Digital Converter .. 123 5.2 ESD Ratings ........................................ 44 7.3 General-Purpose Input/Output ..................... 134 5.3 Power-On Hours (POH) ............................. 44 7.4 Enhanced Next Generation High-End Timer 5.4 Recommended Operating Conditions ............... 45 (N2HET) ............................................ 135 5.5 Switching Characteristics for Clock Domains ....... 46 7.5 Controller Area Network (DCAN) .................. 140 5.6 Wait States Required ............................... 46 7.6 Local Interconnect Network Interface (LIN) ........ 141 5.7 Power Consumption ................................. 47 7.7 Serial Communication Interface (SCI) ............. 142 5.8 Input/Output Electrical Characteristics .............. 48 7.8 Inter-Integrated Circuit (I2C) ....................... 143 5.9 Thermal Resistance Characteristics ................ 49 7.9 Multibuffered / Standard Serial Peripheral 5.10 Output Buffer Drive Strengths ...................... 50 Interface ............................................ 146 5.11 Input Timings ........................................ 51 7.10 Ethernet Media Access Controller ................. 158 5.12 Output Timings ...................................... 51 7.11 Universal Serial Bus (USB) Host and Device Controllers ......................................... 162 5.13 Low-EMI Output Buffers ............................ 53 8 Device and Documentation Support .............. 164 6 System Information and Electrical Specifications ........................................... 55 8.1 Device Support ..................................... 164 6.1 Device Power Domains ............................. 55 8.2 Documentation Support ............................ 166 6.2 Voltage Monitor Characteristics ..................... 56 8.3 Related Links ...................................... 166 6.3 Power Sequencing and Power On Reset ........... 57 8.4 Community Resources ............................. 166 6.4 Warm Reset (nRST) ................................. 59 8.5 Trademarks ........................................ 166 6.5 ARM Cortex-R4F CPU Information ................. 60 8.6 Electrostatic Discharge Caution ................... 166 6.6 Clocks ............................................... 64 8.7 Glossary ............................................ 167 6.7 Clock Monitoring .................................... 72 8.8 Device Identification Code Register ............... 167 6.8 Glitch Filters ......................................... 74 8.9 Die Identification Registers ....................... 168 6.9 Device Memory Map ................................ 75 8.10 Module Certifications ............................... 169 6.10 Flash Memory ....................................... 83 9 Mechanical Packaging and Orderable Information ............................................. 174 6.11 Tightly Coupled RAM (TCRAM) Interface Module .. 86 9.1 Packaging Information ............................. 174 6 Table of Contents Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
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