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XRM44L520PGET Datasheet(PDF) 7 Page - Texas Instruments |
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XRM44L520PGET Datasheet(HTML) 7 Page - Texas Instruments |
7 / 158 page RM44L920, RM44L520 www.ti.com SPNS229B – OCTOBER 2014 – REVISED NOVEMBER 2015 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the technical changes made to the SPNS229A device-specific data manual to make it an SPNS229B revision. Scope: Applicable updates to the RM44Lx20 device family, specifically relating to the RM44L920 and RM44L520 devices (Silicon Revision A), which are now in the production data (PD) stage of development have been incorporated. Changes from November 13, 2014 to October 31, 2015 (from A Revision (November 2014) to B Revision) Page • GLOBAL: Deleted RM44L922 and RM44L522 devices; no longer supported ................................................ 1 • Section 1.1 (Features): Updated/Changed the N2HET feature ................................................................. 1 • Section 1.1: Removed ZWT package; no longer supported [along with ZWT performance characteristics] and limited PGE package performance to 180 MHz .................................................................................. 1 • Section 1.3 (Description): Corrected DMA description, 32 peripheral requests, not 32 control packets .................. 4 • Section 1.3: Updated/Changed ESM paragraph ................................................................................. 4 • Table 3-1 (RM44Lx20 Device Comparison): Added RM46L852PGE device column ........................................ 9 • Table 3-1: Deleted RM48L952ZWT device column .............................................................................. 9 • Table 3-1: Updated/Changed the GPIO pin count for PZ package devices from "55" to "45" ............................. 9 • Section 4.2 (Signal Descriptions): Updated/Changed "Default Pull Type" to "Reset Pull Type" .......................... 12 • Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET)): Updated/Changed N2HET1 time input capture or output compare pin description ................................................................................................ 14 • Table 4-2: Updated/Changed N2HET2 time input capture or output compare pin description ........................... 14 • Table 4-5 (PGE Enhanced Pulse-Width Modulator Modules (ePWM)): Updated/Changed EPWM1SYNCI ............ 16 • Table 4-15 (PGE Test and Debug Modules Interface): Updated/Changed TEST pin description ........................ 21 • Table 4-20 (PZ Enhanced High-End Timer Modules (N2HET)): Updated/Changed N2HET1 time input capture or output compare pin description .................................................................................................... 23 • Table 4-23 (PZ Enhanced Pulse-Width Modulator Modules (ePWM)): Updated/Changed EPWM1SYNCI ............. 24 • Table 4-32 (PZ Test and Debug Modules Interface): Updated/Changed TEST pin description .......................... 29 • Table 4-41 (Selectable 8mA/2mA Control): ...................................................................................... 36 • Section 5.1 (Absolute Maximum Ratings): Moved Storage temperature range back to Absolute Maximum Ratings table. ........................................................................................................................ 37 • Added Section 5.3, Power-On Hours (POH) .................................................................................... 37 • Section 5.3 (Power-On Hours (POH)): Added associated footnotes ......................................................... 37 • Section 5.6 (Power Consumption Over Recommended Operating Conditions): Updated/Changed I CC TYP and MAX values .......................................................................................................................... 40 • Section 5.6: Updated/Changed the ICCTYP value from "190 mA at 200 MHz" to "170 mA at 180 MHz"................ 40 • Section 5.6: Updated/Changed the ICCMAX value from "330 mA at 200 MHz" to "310 mA at 180 MHz" ............... 40 • Section 5.7 (Thermal Resistance Characteristics): Added new section ..................................................... 41 • Table 5-1 (Thermal Resistance Characteristics (PGE Package)): Added R ΘJA test conditions and added ΨJT ....... 41 • Table 5-2 (Thermal Resistance Characteristics (PZ Package)): Added R ΘJA test conditions and added ΨJT.......... 41 • Section 5.8.1.2 (Wait States Required): Updated/Changed "The TCM flash can support ..." paragraph ............... 43 • Section 6.1 (Device Power Domains): Updated/Changed the core power domains count to "5" ......................... 44 • Section 6.1: Deleted "The logic in the modules ..." NOTE, no longer applicable ........................................... 44 • Table 6-1 (Voltage Monitoring Specifications): Updated/Changed the VMON, VCC low MAX from "1.0" to "1.13" V... 44 • Table 6-4 (Electrical Requirements for nPORRST): Updated/Changed tf(nPORRST) MIN from "500" to "475" ns......... 46 • Table 6-6 (nRST Timing Requirements): Updated/Changed tv(RST) number of cycles from " 2252tc(OSC)" to "2256tc(OSC)" .......................................................................................................................... 47 • Table 6-6: Updated/Changed tf(nRST) MIN from "500" to "475" ns ............................................................. 47 • Section 6.5.1 Added Quantity of Breakpoints and Watchpoints .............................................................. 48 • Table 6-10 (LPO Specifications): Updated/Changed LPO - HF oscillator, untrimmed frequency TYP value from "9.6" to "9" MHz ..................................................................................................................... 53 • Table 6-10: Added LPO - HF oscillator, trimmed frequency MIN/TYP/MAX values ........................................ 53 • Table 6-19 (Glitch Filter Timing Specifications): Updated/Changed nRST, nPORRST, and TEST MIN values from "500" to "475" ns .............................................................................................................. 60 • Table 6-23 (Timing Requirements for Program Flash): Added footnote to terase(bank0), Sector/Bank erase time ........ 68 Copyright © 2014–2015, Texas Instruments Incorporated Revision History 7 Submit Documentation Feedback Product Folder Links: RM44L920 RM44L520 |
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