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MSP430FR4133 Datasheet(PDF) 80 Page - Texas Instruments |
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MSP430FR4133 Datasheet(HTML) 80 Page - Texas Instruments |
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80 / 101 page  1 3 5 7 9 11 13 2 4 6 8 10 12 14 TEST/SBWTCK MSP430FRxxx RST/NMI/SBWTDIO TDO/TDI TCK GND JTAG R1 47 kΩ (see Note B) VCC TOOL VCC TARGET C1 1 nF (see Note B) J1 (see Note A) J2 (see Note A) Important to connect DVCC DVSS V CC MSP430FR4133, MSP430FR4132, MSP430FR4131 SLAS865B – OCTOBER 2014 – REVISED AUGUST 2015 www.ti.com A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or programming adapter. B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is 1.1 nF when using current TI tools. Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) 7.1.4 Reset The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function Register (SFR), SFRRPCR. In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing specifications generates a BOR-type device reset. Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI. When an external NMI event occurs, the NMIIFG is set. The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not. If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-k Ω pullup resistor to the RST/NMI pin with a 1.1-nF pulldown capacitor. The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers. See the device family user’s guide (SLAU367) for more information on the referenced control registers and bits. 7.1.5 Unused Pins For details on the connection of unused pins, see Section 4.4. 80 Applications, Implementation, and Layout Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR4133 MSP430FR4132 MSP430FR4131 |
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