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54F280 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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54F280 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 8 page TLF9512 August 1995 54F74F280 9-Bit Parity GeneratorChecker General Description The ’F280 is a high-speed parity generatorchecker that ac- cepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH If an even number of inputs is HIGH the Sum Even output is HIGH If an odd number is HIGH the Sum Even output is LOW The Sum Odd output is the complement of the Sum Even output Features Y Guaranteed 4000V minimum ESD protection Commercial Military Package Package Description Number 74F280PC N14A 14-Lead (0300 Wide) Molded Dual-In-Line 54F280DM (Note 2) J14A 14-Lead Ceramic Dual-In-Line 74F280SC (Note 1) M14A 14-Lead (0150 Wide) Molded Small Outline JEDEC 74F280SJ (Note 1) M14D 14-Lead (0300 Wide) Molded Small Outline EIAJ 54F280FM (Note 2) W14B 14-Lead Cerpack 54F280LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols Connection Diagrams TLF9512 – 3 IEEEIEC TLF9512 – 5 Pin Assignment for DIP SOIC and Flatpak TLF9512 – 1 Pin Assignment for LCC TLF9512 – 2 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation RRD-B30M115Printed in U S A |
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