Q

1

6

C1

D

CLR

CLK

D

R

3

4

SN74LVC1G175

SCES560G – MARCH 2004 – REVISED JUNE 2015

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8 Detailed Description

8.1 Overview

The SN74LVC1G175 device has an asynchronous clear (CLR) input. When CLR is high, data from the input pin

(D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the

low state, regardless of the clock edge or data on D.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

preventing damaging current backflow through the device when it is powered down.

8.2 Functional Block Diagram

8.3 Feature Description

broad range of systems. The 5.5-V I/Os allow down translation and also allow voltages at the inputs when

8.4 Device Functional Modes

Table 1 lists the functional modes for SN74LVC1G175.

Table 1. Function Table

INPUTS

OUTPUT

Q

CLR

CLK

D

H

↑

L

L

H

↑

H

H

H

H or L

X

L

X

X

L

10

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