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SN74LVC2G14 Datasheet(PDF) 10 Page - Texas Instruments |
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SN74LVC2G14 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 24 page Frequency - MHz 0 20 40 60 80 0 1 2 3 4 5 6 7 8 9 10 D003 Icc 1.8V Icc 2.5V Icc 3.3V Icc 5V SN74LVC2G14 SCES200O – APRIL 1999 – REVISED AUGUST 2015 www.ti.com Typical Application (continued) 9.2.3 Application Curve Figure 5. ICC vs Frequency 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1- μF capacitor. If there are multiple VCC pins, then TI recommends a 0.01-μF or 0.022- μF capacitor for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1- μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input terminals should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. The following rules must be observed under all circumstances: • All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. • The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more convenient. 10 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC2G14 |
Similar Part No. - SN74LVC2G14_15 |
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