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SAB82525H Datasheet(PDF) 26 Page - Infineon Technologies AG |
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SAB82525H Datasheet(HTML) 26 Page - Infineon Technologies AG |
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26 / 126 page  Semiconductor Group 26 82525 82526 82525 82526 SAB SAB SAF SAF 2.6 Receive Data Flow (Summary) The following figure gives an overview of the management of the received HDLC frames as affected by different operating modes. Figure 8 Receive Data Flow of HSCX ITD00228 FLAG ADDR CTRL Ι CRC FLAG ADDRESS CONTROL DATA STATUS Auto/16 RAH1, 2 RAL1, 2 RFIFO RHCR RSTA 001 ADM MDS0 MDS1 RSTA RHCR RFIFO X RAL1, 2 0 0 0 Auto/8 Auto/16 011 RAH1, 2 RAL1, 2 RFIFO RHCR RSTA Auto/8 010 X RFIFO RHCR RSTA Transparent 101 RAH1, 2 RFIFO RHCR RSTA 100 RFIFO RSTA Non Non RAL1, 2 RAL1 1 0 Transparent RAL1 RHCR MODE Note: In case of on 8 Bit Address, the Control Field starts here! Description of Symbols: Compared with (register) Processed autonomously Stored (FIFO, register) |
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