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SAB82525H Datasheet(PDF) 5 Page - Infineon Technologies AG |
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SAB82525H Datasheet(HTML) 5 Page - Infineon Technologies AG |
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5 / 126 page  General Information Semiconductor Group 5 Advanced CMOS technology Low power consumption: active 25 mW at 4 MHz standby 4 mW General The SAB 82525 is a High-Level Serial Communication Controller compatible to the SAB 82520 HSCC with extended features and functionality (HSCX). The SAB 82526 is pin and software compatible to the SAB 82525, realizing one HDLC channel (channel B). The HSCX has been designed to implement high-speed communication links using HDLC protocols and to reduce the hardware and software overhead needed for serial synchronous communications. Due to its 8-bit demultiplexed adaptive bus interface it fits perfectly into every Siemens/Intel or Motorola 8- or 16-bit microcontroller or microprocessor system. The data through-put from/to system memory is optimized transferring blocks of data (usually 32 bytes) by means of DMA or interrupt request. Together with the storing capacity of up to 64 bytes in on-chip FIFO’s, the serial interfaces are effectively decoupled from the system bus which drastically reduces the dynamic load and reaction time of the CPU. The HSCX directly supports the X.25 LAPB, the ISDN LAPD, and SDLC (normal response mode) protocols and is capable of handling a large set of layer-2 protocol functions independently from the host processor. Furthermore, the HSCX opens a wide area for applications which use time division multiplex methods (e.g. time-slot oriented PCM systems, systems designed for packet switching, ISDN applications) by its programmable telecom-specific features. The HSCX is fabricated using Siemens advanced ACMOS 3 technology and available in a P-LCC-44 pin package. The data link controller handles all functions necessary to establish and maintain an HDLC data link, such as – Flag insertion and detection, – Bit stuffing, – CRC generation and checking, – Address field recognition. Associated with each serial channel is a set of independent command and status registers (SP-REG) and 64-byte deep FIFO’s for transmit and receive direction. DMA capability has been added to the HSCX by means of a 4-channel DMA interface (SAB 82525) with one DMA request line for each transmitter and receiver of both channels. |
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