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SAB82532H Datasheet(PDF) 93 Page - Siemens Semiconductor Group |
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SAB82532H Datasheet(HTML) 93 Page - Siemens Semiconductor Group |
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93 / 272 page  SAB 82532/SAF 82532 Serial Interface (layer-1 functions) Semiconductor Group 93 07.96 allowed a second bus access. When ten consecutive ‘1’s have been detected, transmission is allowed again and the priority class is increased (to eight ‘1’s). Inside a priority class, the order of transmission (individual priority) is based on the HDLC address, as explained in the preceding paragraph. Thus, when a collision occurs, it is always the station transmitting the only ‘zero’ (i.e. all other stations transmit a ‘one’) in a bit position of the address field that wins, all other stations cease transmission immediately. 8.3.4 Timing Modes If a bus configuration has been selected, the ESCC2 provides two timing modes, differing in the time interval between sending data and evaluation of the transmitted data for collision detection. 1. Timing mode 1 (CCR0: SC1, SC0 = ‘01’) Data is output with the rising edge of the transmit clock via the TxD pin, and evaluated 1/2 a clock period later at the CxD pin with the falling clock edge. 2. Timing mode 2 (CCR0: SC1, SC0 = ‘11’) Data is output with the falling clock edge and evaluated with the next falling clock edge. Thus one complete clock period is available between the instant when data is output and collision detection. 8.3.5 Functions of RTS Output In clock modes 0, 1 and 4, the RTS output can be programmed via CCR2 (SOC bits) to be active when data (frame or character) is being transmitted. This signal is delayed by one clock period with respect to the data output TxD, and marks all data bits that could be transmitted without collision. In this way a configuration may be implemented in which the bus access is resolved on a local basis (collision bus) and where the data are sent one clock period later on a separate transmission line. Figure 41 Request-to-Send in Bus Operation Note: For details on the functions of the RTS pin refer to chapter 8.5. |
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