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SAB82538H-10 Datasheet(PDF) 43 Page - Infineon Technologies AG |
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SAB82538H-10 Datasheet(HTML) 43 Page - Infineon Technologies AG |
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43 / 253 page  SAB 82538 SAF 82538 Semiconductor Group 43 Interrupt priority mode 3: Rotating priority of 7 channels With IVA.ROT = 1 and IPC.ROTM = 1 the priority adjustment is performed only on 7 channels while one channel is fixed to the highest priority level. As described in “Interrupt Priority Mode 1” for fixed priority scheme, selection of the “highest priority” channel is simply done with every write access to the IVA register in conjunction with the channel assigned IVA register address: IVA Register Address: Highest Priority Channel 38H 0 78H 1 B8H 2 F8H 3 138H 4 178H 5 1B8H 6 1F8H 7 If the highest priority channel generates an interrupt and gets serviced by reading the interrupt vector or the interrupt status register of that channel a reordering of the other channels will not take place. The dynamic adjustment of the channel priorities does not affect the interrupt group of an interrupt even if it is the highest priority channel. Example: Let the channel priorities be labeled as follows with channel “2” as fixed highest priority channel: 2 5 6 7 01 34 pp in descending order. Supposing the channel labeled “7” generates an interrupt which is serviced because no unmasked higher priority is pending, the channels will be reordered as follows: 2 0 1 3 45 67 pp Even if the same channel generates another interrupt, it will not be serviced before at least one other channel (if any) requesting service by that time. If the channel labeled “2” now generates an interrupt which gets serviced the order is to be the same as above: 2 0 1 3 45 67 pp Note: Parallel ports have always lowest priority. |
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