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SAB82532N-10 Datasheet(PDF) 80 Page - Siemens Semiconductor Group |
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SAB82532N-10 Datasheet(HTML) 80 Page - Siemens Semiconductor Group |
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80 / 272 page  SAB 82532/SAF 82532 Serial Interface (layer-1 functions) Semiconductor Group 80 07.96 8 Serial Interface (layer-1 functions) The two serial interfaces of the ESCC2 provide two fully independent communication channels, supporting layer-1 functions to a high degree by various means of clock generation and clock recovery. Note: Since the two serial channels are completely independent, the functions described in this document apply to both channels A and B. For simplification purposes the indices A and B will usually be omitted from the signal names, and are implied. 8.1 Clock Modes The ESCC2 includes an internal Oscillator (OSC) as well as independent Baud Rate Generator (BRG) and Digital Phase Locked Loop (DPLL) circuitry for each serial channel. The transmit and receive clock can be generated either • externally, and supplied via the RxCLK and/or TxCLK pins, or • internally, by means of the – OSC and/or BRG, and – DPLL, recovering the receive (and optionally transmit) clock from the received data stream. There are a total of 8 different clocking modes programmable via the CCR1 register, providing a wide variety of clock generation and clock pin functions, as shown in table 4: Table 4 Overview of Clock Modes Clock Type Source Generation Mode Receive Clock RxCLK Pins DPLL OSC BRG Externally Internally 0, 1, 5 2, 3a, 6, 7a 4 3b, 7b Transmit Clock TxCLK Pins RxCLK Pins DPLL BRG ./.16 OSC BRG Externally Internally 0a, 2a, 6a 1,5 3a, 7a 2b, 6b 4 0b, 3b, 7b |
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