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SAB82532N Datasheet(PDF) 57 Page - Siemens Semiconductor Group |
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SAB82532N Datasheet(HTML) 57 Page - Siemens Semiconductor Group |
57 / 272 page SAB 82532/SAF 82532 HDLC/SDLC Serial Mode Semiconductor Group 57 07.96 Examples The interaction between ESCC2 and the CPU during transmission and reception of I-frames is illustrated in figure 26a, the flow control with RR/RNR during reception of I-frames in figure 26b, and during transmission of I-frames in figure 27a. Both, the sequence of the poll cycle and protocol errors are shown in figure 27b. Figure 26a Figure 26b Transmission/Reception I-Frames Flow Control/Transmission Figure 27a Figure 27b Flow Control/Reception S-Commands/Protocol Error |
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