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VX6953CB Datasheet(PDF) 27 Page - STMicroelectronics |
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VX6953CB Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 107 page  8209023 Rev 5 27/107 VX6953CB Functional description 3.5.3 Clock input type As required by the SMIA specification the VX6953CB can receive the clock types shown in Figure 10. The clock is fail-safe/high impedance when in either AC or DC coupled and in any mode including the power off state. The pad has a SCHMITT TRIGGER input. Figure 10. Clock input types 3.6 Control and video interface formats Image data is transferred from the VX6953CB using a high speed subLVDS serial link.The serial control data is transferred to and from the VX6953CB on a CCI bus. • Video maximum link speeed: 640 Mbps for CCP2 and 800 Mbps for CSI-2. • CCI command speed: from 100 KHz to 400 KHz. 3.6.1 CCP serial data link Data signals (DATA+ and DATA-) and clock signals (CLK+ and CLK-) are transferred from VX6953CB on two pairs of balanced 100 Ω impedance transmission lines. The transmission line pairs and custom transmitters/receivers realize a very low voltage differential (subLVDS) signalling scheme that can transfer information in a potentially noisy environment. As implemented in VX6953CB, the CCP link supports the transmission of raw bayer data at 5.0 Mpixel resolution up to 11.5 frame/s at 10-bit resolution (with de-rating). Pad Pad Extclk extclk Camera module Host processor Pad Pad Extclk extclk Camera module Host processor Pad Pad Extclk extclk Camera module Host processor Pad Pad Extclk extclk Camera module Host processor 1st option 2nd option pwrdn pwrdn pwrdn pwrdn pwrdn pwrdn pwrdn pwrdn DC-coupled AC-coupled 3rd option DC-coupled and filtered 4th option AC-coupled and filtered |
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Similar Description - VX6953CB |
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