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SN74LV8154PWG4 Datasheet(PDF) 3 Page - Texas Instruments |
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SN74LV8154PWG4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 20 page CLKA CLKB GAL GAU GBL GBU RCLK RCOA CLKBEN GND VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 CCLR 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SN74LV8154 www.ti.com SCLS589A – AUGUST 2004 – REVISED OCTOBER 2015 5 Pin Configuration and Functions N or PW Package 20-Pin PDIP or TSSOP Top View Pin Functions PIN I/O DESCRIPTION NAME NO. CCLR 11 I Clock clear, asyncrounous active-low clear for both counters CLKA 1 I Clock A, rising edge count clock CLKB 2 I Clock B, rising edge count clock CLKBEN 9 I Clock B enable, acitive-low allows clocking for counter B; connect to RCOA for 32-bit counter. GAL 3 I Gate A lower byte, acitve-low puts lower byte of stored counter A on the Y bus. GAU 4 I Gate A upper byte, acitve-low puts upper byte of stored counter A on the Y bus. GBL 5 I Gate B lower byte, acitve-low puts lower byte of stored counter B on the Y bus. GBU 6 I Gate B upper byte, acitve-low puts upper byte of stored counter B on the Y bus. GND 10 — Ground RCLK 7 I Register Clock, rising edge stores counters into an internal storage register Ready case overflow A, active low when counter A is full count and ready to overflow on next RCOA 8 O clock A VCC 20 — Power supply pin Y0 19 O Data output bit 0 (LSB) Y1 18 O Data output bit 1 Y2 17 O Data output bit 2 Y3 16 O Data output bit 3 Y4 15 O Data output bit 4 Y5 14 O Data output bit 5 Y6 13 O Data output bit 6 Y7 12 O Data output bit 7 (MSB) Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SN74LV8154 |
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