TLF9496

November 1994

54F74F192

UpDown Decade Counter

with Separate UpDown Clocks

General Description

The ’F192 is an updown BCD decade (8421) counter Sep-

arate Count Up and Count Down Clocks are used and in

either counting mode the circuits operate synchronously

The outputs change state synchronously with the LOW-to-

HIGH transitions on the clock inputs

Separate Terminal Count Up and Terminal Count Down out-

puts are used as the clocks for a subsequent stage without

extra logic thus simplifying multistage counter designs Indi-

vidual preset inputs allow the circuit to be used as a pro-

grammable counter Both the Parallel Load (PL) and the

Master Reset (MR) inputs asynchronously override the

clocks

Features

Y

Guaranteed 4000V minimum ESD protection

Commercial

Military

Package

Package Description

Number

74F192PC

N16E

16-Lead (0300 Wide) Molded Dual-In-Line

54F192DM (Note 2)

J16A

16-Lead Ceramic Dual-In-Line

74F192SC (Note 1)

M16A

16-Lead (0150 Wide) Molded Small Outline JEDEC

74F192SJ (Note 1)

M16D

16-Lead (0300 Wide) Molded Small Outline EIAJ

54F192FM (Note 2)

W16A

16-Lead Cerpack

54F192LM (Note 2)

E20A

20-Lead Ceramic Leadless Chip Carrier Type C

Note 1

Devices also available in 13

Note 2

Logic Symbols

Connection Diagrams

TLF9496 – 3

IEEEIEC

TLF9496 – 6

Pin Assignment for

DIP SOIC and Flatpak

TLF9496 – 1

Pin Assignment

for LCC

TLF9496 – 2

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M75Printed in U S A