PEB 20570/PEF 20570

PEB 20571/PEF 20571

Addendum to “DELIC Clock System Synchronization”

Addendum

2/8

2003-08-04

1.1

Clocking the VIP in LT-T Mode by DELIC Layer 1 Clock

Figure 1

Clocking the VIP by using DELIC Layer 1 Clock

When the Central Office is activated, its clock signal is retrieved by the RxPLL of the VIP

and a 1.536 MHz reference signal is generated and used as input signal for the DELIC

DCXO (pin XCLK). This signal is divided down to 8 kHz and used as input for the DCXO

phase detector (PD). The second input to PD is another 8 kHz signal which originates

from the 16.384 MHz output of the DCXO.

The DELIC PLL multiplies the 16.384 MHz DCXO signal up to 61.44 MHz. A divider

generates the 15.36 MHz layer 1 clock which is used to clock the VIP.

When the Central Office is deactivated, the VIP takes its oscillator signal of 15.36 MHz

(the DELIC Layer 1 clock) divided by 10 and uses this signal as DELIC XCLK input as

replacement of the Central Office clock.

As a consequence, the DELIC DCXO gets its own signal as input for the PD. Since the

second PD input is also generated by the DCXO, the PLL system is unstable. This

results in the DCXO and the PLL running to its respective corner frequency. Therefore,

the 100 ppm clock accuracy, required by ITU-T I.430, cannot be guaranteed during this

time. When switching to another clock source (REFCLK), the DELIC DCXO will work

properly again.

DE LIC _refclk1

VIP

C entra l

Offic e

OS C

Rx P L L

DC X O

/1 0

Mu x

15.3 6 M H z

16.384 M H z

Divid e r

PD

PL L

D iv ider

1.5 36 M H z

D ivider

8k H z

XC L K

RE FCL K

16.384 M H z

DE LIC

L1 _C LK

IN C L K

MU X

RE F C L K