Unused Input

Input

Output

Output

Input

Unused Input

LVC

AUP

LVC

3.3-V

0%

20%

40%

60%

80%

100%

AUP

AUP

3.3-V

0%

20%

40%

60%

80%

100%

SN74AUP1T17

SCES803A – APRIL 2010 – REVISED JUNE 2015

www.ti.com

Typical Application (continued)

9.2.3 Application Curves

Figure 4 and Figure 5 show the power consumption with the AUP family.

(1) Single, dual, and triple gates

(1) Single, dual, and triple gates

Figure 4. Static-Power Consumption (µA)

Figure 5. Dynamic-Power Consumption (pF)

10 Power Supply Recommendations

The power supply can be any voltage between the min and max supply voltage rating located in the

Recommended Operating Conditions table.

supply a 0.1-

μF capacitor is recommended and if there are multiple Vcc pins then a 0.01-μF or 0.022-μF

capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different

frequencies of noise. 0.1-

μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be

installed as close to the power pin as possible for best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions

of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only

3 of the 4 buffer gates are used. Such input terminals should not be left unconnected because the undefined

voltages at the outside connections result in undefined operational states. Specified below are the rules that must

be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or

low bias to prevent them from floating. The logic level that should be applied to any particular unused input

depends on the function of the device. Generally they will be tied to Gnd or Vcc whichever make more sense or

is more convenient.

11.2 Layout Example

Figure 6. Layout Example Schematic

10

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