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SN74LV06AD Datasheet(PDF) 7 Page - Texas Instruments |
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SN74LV06AD Datasheet(HTML) 7 Page - Texas Instruments |
7 / 23 page A Y tPHL tPLH VCC 0 V Input VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES From Output Under Test CL (see Note A) Test Point LOAD CIRCUIT FOR OPEN-DRAIN OUTPUTS 50% VCC 50% VCC RL = 1 k Output VCC VOL ≈VCC 50% VCC VOL + 0.3 V 7 SN54LV06A, SN74LV06A www.ti.com SCES336J – MAY 2000 – REVISED JANUARY 2016 Product Folder Links: SN54LV06A SN74LV06A Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated 7 Parameter Measurement Information A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. C. The outputs are measured one at a time, with one input transition per measurement. Figure 3. Load Circuit and Voltage Waveforms 8 Detailed Description 8.1 Overview These hex inverter buffers/drivers are designed for 2-V to 5.5-V VCC operation. The SN74LV06A device performs the Boolean function Y = A in positive logic. The open-drain output require pull-up resistors to perform correctly and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back-flow through the devices when they are powered down. 8.2 Functional Block Diagram Figure 4. Logic Diagram (Positive Logic) |
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