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PEF20550 Datasheet(PDF) 8 Page - Infineon Technologies AG

Part # PEF20550
Description  ICs for Communications
Download  407 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEF20550 Datasheet(HTML) 8 Page - Infineon Technologies AG

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PEB 20550
Table of Contents
Page
Semiconductor Group
8
01.96
4.8.7
D-Channel Enable Register IOM-Port 3 (DCE3) . . . . . . . . . . . . . . . . . . .189
4.8.8
Transmit D-Channel Address Register (XDC) . . . . . . . . . . . . . . . . . . . . .189
4.8.9
Broadcast Group IOM-port 0 (BCG0) . . . . . . . . . . . . . . . . . . . . . . . . . . .190
4.8.10
Broadcast Group IOM-port 1 (BCG1) . . . . . . . . . . . . . . . . . . . . . . . . . . .190
4.8.11
Broadcast Group IOM-port 2 (BCG2) . . . . . . . . . . . . . . . . . . . . . . . . . . .190
4.8.12
Broadcast Group IOM-port 3 (BCG3) . . . . . . . . . . . . . . . . . . . . . . . . . . .190
5
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
5.1.1
IOM® and SLD Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
5.2
Configuration of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
5.2.1
PCM Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
5.2.1.1
PCM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
5.2.1.2
PCM Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
5.2.1.3
PCM Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
5.2.2
Configurable Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
5.2.2.1
CFI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
5.2.2.2
CFI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
5.2.2.3
CFI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
5.3
Data and Control Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
5.3.1
Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
5.3.2
Indirect Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
5.3.3
Memory Access Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
5.3.3.1
Access to the Data Memory Data Field . . . . . . . . . . . . . . . . . . . . . . . . . .244
5.3.3.2
Access to the Data Memory Code (Tristate) Field . . . . . . . . . . . . . . . . . .248
5.3.3.3
Access to the Control Memory Data Field . . . . . . . . . . . . . . . . . . . . . . . .251
5.3.3.4
Access to the Control Memory Code Field . . . . . . . . . . . . . . . . . . . . . . .253
5.4
Switched Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
5.4.1
CFI - PCM Timeslot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
5.4.2
Subchannel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
5.4.3
Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
5.4.3.1
CFI - CFI Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
5.4.3.2
PCM - PCM Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
5.4.4
Switching Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
5.4.4.1
Internal Procedures at the Serial Interfaces . . . . . . . . . . . . . . . . . . . . . .276
5.4.4.2
How to Determine the Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
5.4.4.3
Example: Switching of Wide Band ISDN Channels with the ELIC® . . . . . . 281
5.5
Preprocessed Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
5.5.1
Initialization of Preprocessed Channels . . . . . . . . . . . . . . . . . . . . . . . . .285
5.5.2
Control/Signaling (CS) Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
5.5.2.1
Registers used in Conjunction with the CS Handler . . . . . . . . . . . . . . . .299
5.5.2.2
Access to Downstream C/I and SIG Channels . . . . . . . . . . . . . . . . . . . .301
5.5.2.3
Access to the Upstream C/I and SIG Channels . . . . . . . . . . . . . . . . . . .302


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