PEB20542 datasheet(64/300 Pages) INFINEON

Part #	PEB20542

Description	2 Channel Serial Optimized Communication Controller with DMA

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Manufacturer	INFINEON [Infineon Technologies AG]

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PEB 20542

PEF 20542

Functional Overview

Data Sheet

64

2000-09-14

3.2.3.7

Clock Mode 5b (Octet Sync Mode)

This operation mode has been designed for applications using Octet Synchronous PPP.

It is based on clock mode 5a, but only 8-bit (octet) wide time slot operation is supported,

i.e. bits TTSA1.TEPCM and RTSA1.REPCM must be set to ’1’. Clock mode 5b provides

octet alignment to time slots if Octet Synchronous PPP protocol mode or extended

transparent mode is selected.

Note: For correct operation NRZ data coding/encoding should be used.

The receive and transmit clocks are separate and must be supplied at pins RxCLK and

TxCLK. The SCC receives and transmits only during fixed octet wide time-slots of

programmable location with respect to the octet synchronization signals (via pins OSR

and OST)

The time-slot locations can be programmed independently for receive and transmit

direction via registers TTSA0..TTSA3 / RTSA0..RTSA3 and PCMTX0..PCMTX3 /

PCMRX0..PCMRX3.

Figure 23 shows how to select one or more octet wide time-slots.

Bit ’TSCM’ in register CCR1H determines whether the internal counters are continuously

running even if no synchronization pulse is detected at OST/OSR signals or stopping at

their maximum value.

In the continuous case the repetition rate of operation is 1024 transmit or receive clocks

respectively. An OST/OSR pulse detected earlier resets the corresponding offset

counter and starts operation again.

In the non-continuous case the transmit/receive time slot assigner offset counter is

stopped after the counter reached its maximum value and is started again if an OST/

OSR pulse is detected.

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