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PEB20542 Datasheet(PDF) 4 Page - Infineon Technologies AG |
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PEB20542 Datasheet(HTML) 4 Page - Infineon Technologies AG |
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4 / 300 page 
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com PEB 20542 Revision History: 2000-09-14 DS 1 Previous Version: MISTRAL V1.1 Preliminary Data Sheet, 08.99, DS1 Page (previous Version) Page (current Version) Subjects (major changes since last revision) 34-36 36-38 Correction: signal ’OSR’ is multiplexed with signal ’CD’, signal ’OST’ is multiplexed with ’CTS’ (was vice versa) 85 87 corrected HDLC receive address recognition table 218, 226 222, 230 Corrected location of TCD interrupt (async/bisync modes only) in registers ISR0 and IMR0 from bit 7 to bit 2. - - removed referneces to Intel Multiplexed Mode 268 272 Chapter "Electrical Characteristics" updated with final characterization results. |
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