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PEB20532 Datasheet(PDF) 83 Page - Infineon Technologies AG |
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PEB20532 Datasheet(HTML) 83 Page - Infineon Technologies AG |
83 / 282 page PEB 20532 PEF 20532 Detailed Protocol Description Data Sheet 83 2000-09-14 4.1 HDLC/SDLC Protocol Modes The HDLC controller of each serial channel (SCC) can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and the address recognition features can be performed in a very flexible way satisfying almost any application specific requirements. There are 4 different HDLC operating modes which can be selected via register bits CCR2L:MDS[1:0] and CCR2L:ADM. 4.1.1 HDLC Submodes Overview The following table provides an overview of the different address comparison mechanisms in HDLC operating modes: 4.1.1.1 Automode Characteristics: Window size 1, random message length, address recognition. The SCC processes autonomously all numbered frames (S-, I-frames) of an HDLC protocol. The HDLC control field, I-field data of the frames and an additional status byte are temporarily stored in the SCC receive FIFO. Table 13 Address Comparison Overview Mode Address Field Recognized Address Bytes for a Match: High Address Byte Low Address Byte Address Mode 2 - Auto Mode 16 bit FE H / FCH (1111 11 C/R 02) and RAL1 FE H / FCH (1111 11 C/R 02) and RAL2 RAH1 and RAL1 RAH1 and RAL2 RAH2 and RAL1 RAH2 and RAL2 8 bit RAL1 don’t care RAL2 don’t care Address Mode 1 8 bit FE H / FCH (1111 11 C/R 02) don’t care RAH1 don’t care RAH2 don’t care Address Mode 0 None don’t care don’t care |
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