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PEF20324 Datasheet(PDF) 7 Page - Infineon Technologies AG |
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PEF20324 Datasheet(HTML) 7 Page - Infineon Technologies AG |
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7 / 63 page  PEB 20324 PEF 20324 Introduction Hardware Reference Manual 7 04.99 1 Introduction The MUNICH128X is a 128-channel WAN Protocol Controller which provides four independent 24/32-channel HDLC controllers, each with a dedicated 64-channel DMA Controller and a Serial PCM Interface Controller. The device is offered in a 160- pin MQFP package, making it ideal for high-port-density applications. The MUNICH128X provides capability for up to 128 full duplex serial PCM channels. The chip performs layer 2 HDLC formatting/deformatting or V.110 or X.30 protocols up to a data rate of 38.4 kbit/s (V.110) or 64 kbit/s (HDLC). The MUNICH128X also performs transparent transmission for DMI modes 0, 1, and 2. Processed data is transferred to host memory via the PCI interface or de-multiplexed bus interface. The MUNICH128X is compatible with the LAPD ISDN (Integrated Services Digital Network) protocol specified by CCITT, as well as with HDLC, SDLC, LAPB and DMI protocols. It provides rate adaptation for time slot transmission from 64 kbit/s down to 8 kbit/s and the concatenation of time slots, supporting the ISDN H0, H11, H12 superchannels. Figure 1-1 Simplified Block Diagram ITB10007 Serial Interface Interface Interface Interface Protocol Controller Controller Protocol Controller Protocol Controller Protocol Controller DMA Controller DMA Controller DMA Controller DMA PCI Interface/DEMUX BUS Address/Data Control PCM PCM PCM PCM Serial Serial Serial |
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